By

Dr. John P. Abraham

University of Texas – Pan American

CSCI 6380	ARRANGED
CSCI 6390	ARRANGED
Office Hours	M 8:30-9:00 PM	Please make appointment	For evening students only
OFFICE HOURS	T 8:30-9:00 PM	Please make appointment	For evening students only
OFFICE HOURS	M 9:30 - 11:30 AM
OFFICE HOURS	Th 9:00-12:00 NOON
CSCI 6315 Applied Database Systems	M 5:45 - 8:25 PM	Syllabus
CSCI 6335 Advanced Computer Architecture	T 5:45 – 8:25 PM	Syllabus	Ppt1 ppt2 ppt3 ppt4 ppt5
ELEE 6335 Advanced Computer Architecture	T 5:45 – 8:25 PM	SyllabusEE
CSCI 4390 Senior Project	BY APPOINTMENT

Teaching Assistant: Mr. Sebastian Puthenpurayil. All homework and lab related assignments will be handled by the TA.

Email for the TA – smputhenpur@panam.edu

Web http://cs.panam.edu/~sebastian/

Kyewook Lee, Tele: 956-661-9103. email: kyewooklee@hotmail.com. Kyewook Lee will be responsible for Oracle related teaching and laboratory assignments.

Textbook:

Computer Architecture: A Quantitative Approach, David A Patterson and John L. Hennessy, 3rd Edition, 2003, Morgan Kaufmann Publishers. This and the previous editions of this book are considered to be one of the most quoted and comprehensive book on computer architecture available today. It is widely used in universities around the world and extensively used by chip researchers and manufacturers.

Prerequisites:

Students must have taken either CSCI 4335 or CSCI 6300 or its equivalent. If you have not completed one of these courses but have sat through the entire material, you may attempt this course. Either CSCI 2333 or its equivalent or an equal understanding of Assembly Language programming.

Course Content:

This is an advanced look at Computer Architecture concentrating primarily on the implementation of RISC instruction sets, pipelining, instruction-level and block-level paralellism. As opposed to CSCI 6300 where the emphasis was on architectural components, the emphasis here is on CPU and memory design to improve efficiency. Topics are examined at both the instruction set level and the hardware level. The course will take a quantitative approach when describing these topics to provide a mechanism for evaluating how useful the various ideas are. Other topics in the course will include cache and main memory system.

Course Objectives:

The goal of this course is to provide graduate students a comprehensive understanding of computer architecture issues and concerns from the perspective of modern personal computers, RISC workstations and mainframes. The student should be able to critically evaluate a computer's performance based on its instruction set architecture, the degree of pipelining and parallelism, its memory subsystem and I/O.

Course Assignments and Grading:

There will be one midterm and one final examination. These exams will constitute 60% of the grade. 25% of the grade will be for the assignment administered by my TA. The TA will be totally responsible for this portion of the grade. The remaining 15% of the grade will be for daily quizzes other reading I assign during the semester. Letter grades will be based on the following grading scale A: 90-100% B: 80-89% C: 70-79% F: 0-69%.

For each day of class you will prepare 10 multiple choice questions (along with keys) over the material covered. Please bring two copies of the tests. These questions will be given as daily quizzes. 5 points will be given for good questions and 10 points for correct answers. Only multiple choice questions will be accepted. These quizzes may not be made up. Therefore, it is essential that you come to every class on time. The quizzes are given at the beginning of the class. Students arriving late may turn in their questions, but won’t be allowed to take the quiz.

Chapters covered:

Chapter 1 – Fundamentals of Computer Design. Technology trends and Measuring and Reporting Performance.

Chapter 2 – Instruction set Principles and Examples. Introduction to MIPS architecture

Appendix A – Pipelining –Basic and Intermediate concepts

Chapter 3 – Instruction-Level Parallelism and Dynamic Exploitation.

Chapter 4 – Instruction-Level Parallelism

Chapter 5 – Memory Hierarchy Design

If you must miss an exam, make prior arrangements. No make-up exams will be given unless you contact me in advance! Homeworks may be submitted to me by email or hardcopy in my mailbox prior to class time. Late homeworks will be levied heavy penalties. Penalty: One day late 10%, 1 week late 20%, 2 weeks late 50%. Not accepted afterwards.

Note to students with disabilities: If you have a disability which will make it difficult for you to carry out the work as outlined here, or you need special accommodations/assistance due to a disability, please contact Ruben Garza, Coordinator, at the Office of Services for Students with Disabilities, Emilla Hall, Rm 100, immediately. Appropriate arrangements or accommodations can be arranged.